Extendable instruction set computer

The EISC (Extendable Instruction Set Computer) is a compressed code processor architecture for embedded applications. It has both the properties of RISC architecture, simplicity, and that of CISC processor, expandability. The architecture is developed by Advanced Digital Chips Inc., Seoul, Korea.<http://www.adc.co.kr>

Core introduction

Introduction

EISC stands for "Extendable Instruction Set Computer". EISC processor advantages over existing CISC and RISC architectures: EISC can represent any length of an operand without variable length instruction elimination inefficiencies caused by difficulties in processing variable instruction decoding. EISC architecture maximized cost and performance efficiency and at the same time offers flexibility and power through the Extendable Register and Extension Flag, which increase the code density while allowing a simple 16-bit-based instruction set.[1]

Extension (Extension Register (ER) and Extension Flag (E))

EISC has Extension Register (ER) and Extension Flag (E) for variable-length operand.

Extension Register(ER) : Extension operand is saved in this register.
Extension Flag : This flag is high when Extension Register was stored.
LERI instruction is used when extension operand is stored in Extension Register. The following figure. when using both LERI and LDI(load immediate), shows the operation.
16bit EISC processor
16-bit en
32bit EISC processor
32-bit en
The above figure shows LERI and LDI operation at 16-bit EISC processor and 32-bit EISC processor. Like in the above figure, the Extension Register is expanded as 12-bit length unit at 16-bit EISC Processor and expended as 14-bit length unit at 32-bit EISC processor.

EISC core Feature

EISC 5 step
Small(Small code size, High code density)
EISC is consist of 16bits fixed length instructions which has the short length operand appeared frequently and extends operand by using LERI instructions as the length of operand, then the size of user program can be reduced. Therefore, it has an advantage the code density is higher.
Simple(Simple instruction set, Simple hardware)
The number of instructions in EISC, has 16bits fixed length instruction set, is lower because one Op-code has only one instruction. Namely, it's not required multiple instructions as operand length, so the hardware architecture can be simpler than the other type of microprocessors.
Speed(High speed)
Because of the simple EISC hardware architecture, its operational clock frequency and the performance can be achieved higher.
Scalable(Scalable 16 / 32bit microprocessor architecture)
Since EISC is an architecture aimed at extending the length of operand, the basic OP-code is common throughout the 16 / 32bit architecture, Only a small number of the instruction will be adjusted according to the variation of the register size.
Therefore, EISC is the first architecture that achieves complete scalability.
Saving(Power saving-low power)
A reduction in the logic gate count that consumes power must be achieved to lower consumption at the architecture level. Hardware must have a simple structure and the state of the CMOS logic gate must not change on a frequent basis. Data bus traffic must also be reduced. A high code density architecture is required as program size must be minimal. Compared to other microprocessors, EISC is a low power consumption architecture because of its simple hardware and high code density.

EISC core Architecture

SE1608
SE1608 is a small, high-performance, low power 16bit embedded processor based on Adchips' proprietary EISC(Extendable Instruction Set Computer) architecture.
SE1608 has 7 general purpose registers and 6 special purpose registers, use 16bit fixed length instruction set. Also SE1608 has 16bit barrel shift and 16bit x 16bit 1cycle multiplier. Gate count is about 7K, operation speed is 50MHz on 0.18um process.
EISC SE1608 link
SE3208
SE3208 is a small, high-performance, low power 32bit embedded processor baased on Adchips' proprietary EISC(Extendable Instruction Set Computer) architecture.
SE3208 has 8 general purpose reigisters and 6 special purpose rigisters, use 16bit fixed length instruction set. Also SE3208 has 32bit barrel shift and 32bit x 32bit 1cycle multiplier, Gate count is about 15K, operation speed is 50MHz on 0.18um process.
EISC SE3208 link
AE32000
AE32000 is a small, high-performance, low power 32bit embedded processor baased on Adchips' proprietary EISC(Extendable Instruction Set Computer) architecture.
AE32000 has 16 general purpose reigisters and 7 special purpose rigisters, use 16bit fixed length instruction set. Also AE32000 has 32bit barrel shift and 32bit x 32bit = 64bit multilpier(signed / unsigned) and accumulate. DSP instruction and the DSP X/Y memory equipped with option.
EISC AE32000 link

EISC core Software Tool

Integrated Development Environment for EISC processor
EISC Studio provides convenient source editor, compile and debug tools while user implements a system and also, various images of high-level programming language and source level debugging of executable code.
EISC studio
Integrated Development Environment
Convenient Embedded Editor

Instruction Set Architecture Family

The EISC has 16-bit, 32-bit and 64-bit instruction set architecture family. There exist SE (simple EISC) series and AE (Advanced EISC) series.

Class Core Process Clock Freq. Average IPC Peak MIPS Gate Counts Power Consumption (@0.18 μm) Pipelines SIMD-DSP
SE SE1608 16-bit CPU 70 MHz@0.18 μm 8K 3 stages
SE3208 32-bit CPU 70 MHz@0.18 μm 13K 3 stages
AE AE32000C-Tiny up to 100 MHz@0.18 μm over 0.8 110 MIPS@100 MHz 26-30K under 0.15 mW/MHz 3 stages
AE32000C-Lucida up to 150 MHz@0.18 μm over 0.87 145 MIPS@130 MHz 50-88K under 0.30 mW/MHz 5 stages SIMD-DSP
AE32000C-Empress up to 300 MHz@0.13 μm over 0.78 120K under 0.38 mW/MHz 9 stages SIMD-DSP

See also

References

  1. ↑ EISC ISA link

External links

Related papers

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